test2

Code 테스트

Verilog code 테스트

always @ (posedge clk) begin
  if (rst) r1 <= 1'b0;
  else     r1 <= r2;
end

VHDL Code 테스트

function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER is
  variable result: INTEGER;
begin
  assert ARG'length <= 32
    report "ARG is too large in CONV_INTEGER"
    severity FAILURE;
  result := 0;
  for i in ARG'range loop
    if i /= ARG'left then
      result := result * 2;
      if tbl_BINARY(ARG(i)) = '1' then
        result := result + 1;
      end if;
    end if;
  end loop;
  return result;
end;